The DEK Wafer Handling Station is a fully automated handling solution, integrated with DEK's wafer level mass imaging processes. It is developed in conjunction with Adept Semiconductor Equipment Division; a specialist partner with impeccable credentials. This new handling solution allows you to process wafers up to 200mm from standard, open cassettes with no adjustment necessary. The handling portfolio also includes a turnkey solution for 300mm wafers.


This wafer handling capability is compliant with SMEMA and SEMI S-2 industry standards, and perfectly integrated with our mass imaging technology and processes. Each wafer is unloaded from the cassette onto the wafer chuck for mass imaging. After processing, the wafer can be returned to its original position in the cassette or transferred directly to a reflow oven for in line configuration. Comprehensive features include multi-position loading for up to 6 cassettes, pre-alignment to ± 0.5µm accuracy, windowsbased control interfaces and optional Class 1, 10, 100 clean air source.



Fully integrated handling for mass imaging 150mm, 200mm, 300mm wafers

Use for solder ball placement, paste deposition: all wafer level processes

Multi-position cassette loading up to 6 cassettes

Unloads from cassette to pre-aligner: +/- 0.5 degree theta accuracy

Loaded post-pre-align into standard pallet (wafer chuck system)

Standard SEMI and SMEMA mechanical and electrical interfaces

Windows-based controller and off-line process-flow development

Reflow oven interface input station

Reflow oven interface output station

Lot and wafer tracking (Bar code or OCR)

Single point utility and controls interface

Optional Class 1, 10, 100 clean-air source with internal ULPA filter and distribution ducting.

Optional wafer scanner module (Speeds processing of partially loaded cassettes)

SEMI S-2 compliant; CE/UL certified



The single point utility and controls interface features a Windows-based GUI for intuitive, offline development and optimisation of your process flow. Savings in paste wastage deliver further cost reductions in a process that is already significantly less expensive than first generation approaches to wafer bumping.